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| author | Stafford Horne <shorne@gmail.com> | 2022-02-19 14:48:46 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2022-02-25 15:42:23 +0900 |
| commit | 22991cfbdfacc195b982d3ee12a823e75ded4b29 (patch) | |
| tree | 5156c4b28a773c3ebbfd8e1cd327441024c33bbf /hw/xtensa | |
| parent | 76f36985e54e1ebb2c1907bee75b5f7d778a5902 (diff) | |
| download | qemu-22991cfbdfacc195b982d3ee12a823e75ded4b29.zip qemu-22991cfbdfacc195b982d3ee12a823e75ded4b29.tar.gz qemu-22991cfbdfacc195b982d3ee12a823e75ded4b29.tar.bz2 | |
hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART
Currently the OpenRISC SMP configuration only supports 2 cores due to
the UART IRQ routing being limited to 2 cores. As was done in commit
1eeffbeb11 ("hw/openrisc/openrisc_sim: Use IRQ splitter when connecting
IRQ to multiple CPUs") we can use a splitter to wire more than 2 CPUs.
This patch moves serial initialization out to it's own function and
uses a splitter to connect multiple CPU irq lines to the UART.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/xtensa')
0 files changed, 0 insertions, 0 deletions