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authorCathy Zhang <cathy.zhang@intel.com>2020-04-13 14:52:38 +0800
committerPaolo Bonzini <pbonzini@redhat.com>2020-06-10 12:10:27 -0400
commit353f98c9ad52ff4b8cfe553c90be04f747a14c98 (patch)
tree9bba0c487797641b43e752af185eb3925489d61b /hw/vfio
parentc781a2cc423155079acf45e5ce79e6635f109fc4 (diff)
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x86/cpu: Enable AVX512_VP2INTERSECT cpu feature
AVX512_VP2INTERSECT compute vector pair intersection to a pair of mask registers, which is introduced with intel Tiger Lake, defining as CPUID.(EAX=7,ECX=0):EDX[bit 08]. Refer to the following release spec: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Message-Id: <1586760758-13638-1-git-send-email-cathy.zhang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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