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authorAxel Heider <axel.heider@hensoldt.net>2022-11-19 15:59:40 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-01-05 12:14:43 +0000
commit1ead962edf1297e223a039167429d4c986bfb90e (patch)
tree81445a26e92a2cd04d11183d7e56e4e028137634 /hw/timer
parent018ee7948ff1df9cd98efee6e9d117eadb630cff (diff)
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hw/timer/imx_epit: define SR_OCIF
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer')
-rw-r--r--hw/timer/imx_epit.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 661e915..f148868 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -66,7 +66,7 @@ static const IMXClk imx_epit_clocks[] = {
*/
static void imx_epit_update_int(IMXEPITState *s)
{
- if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
+ if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
@@ -256,9 +256,9 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
break;
case 1: /* SR - ACK*/
- /* writing 1 to OCIF clears the OCIF bit */
- if (value & 0x01) {
- s->sr = 0;
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
+ if (value & SR_OCIF) {
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
imx_epit_update_int(s);
}
break;
@@ -309,8 +309,8 @@ static void imx_epit_cmp(void *opaque)
IMXEPITState *s = IMX_EPIT(opaque);
DPRINTF("sr was %d\n", s->sr);
-
- s->sr = 1;
+ /* Set interrupt status bit SR.OCIF and update the interrupt state */
+ s->sr |= SR_OCIF;
imx_epit_update_int(s);
}