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| author | Daniel Hoffman <dhoff749@gmail.com> | 2023-11-18 15:11:29 -0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-01-19 12:28:10 +0100 |
| commit | c0d0b716ba3e52236088eb9f75ef5cbd7e15a4f3 (patch) | |
| tree | c4f07be814605919f4a05ac2e8f6841e3a62c968 /hw/timer/trace-events | |
| parent | 88cf5fec91e50cd34bc002b633b4116228db0bc8 (diff) | |
| download | qemu-c0d0b716ba3e52236088eb9f75ef5cbd7e15a4f3.zip qemu-c0d0b716ba3e52236088eb9f75ef5cbd7e15a4f3.tar.gz qemu-c0d0b716ba3e52236088eb9f75ef5cbd7e15a4f3.tar.bz2 | |
hw/timer/hpet: Convert DPRINTF to trace events
This conversion is pretty straight-forward. Standardized some formatting
so the +0 and +4 offset cases can recycle the same message.
Signed-off-by: Daniel Hoffman <dhoff749@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231118231129.2840388-1-dhoff749@gmail.com>
[PMD: Fixed few string formats]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/timer/trace-events')
| -rw-r--r-- | hw/timer/trace-events | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 8145e18..de769f4 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -99,3 +99,18 @@ sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address sh_timer_start_stop(int enable, int current) "%d (%d)" sh_timer_read(uint64_t offset) "tmu012_read 0x%" PRIx64 sh_timer_write(uint64_t offset, uint64_t value) "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64 + +# hpet.c +hpet_timer_id_out_of_range(uint8_t timer_id) "timer id out of range: 0x%" PRIx8 +hpet_invalid_hpet_cfg(uint8_t reg_off) "invalid HPET_CFG + %u" PRIx8 +hpet_ram_read(uint64_t addr) "enter hpet_ram_readl at 0x%" PRIx64 +hpet_ram_read_reading_counter(uint8_t reg_off, uint64_t cur_tick) "reading counter + %" PRIu8 " = 0x%" PRIx64 +hpet_ram_read_invalid(void) "invalid hpet_ram_readl" +hpet_ram_write(uint64_t addr, uint64_t value) "enter hpet_ram_writel at 0x%" PRIx64 " = 0x%" PRIx64 +hpet_ram_write_timer_id(uint64_t timer_id) "hpet_ram_writel timer_id = 0x%" PRIx64 +hpet_ram_write_tn_cfg(void) "hpet_ram_writel HPET_TN_CFG" +hpet_ram_write_invalid_tn_cfg(uint8_t reg_off) "invalid HPET_TN_CFG + %" PRIu8 " write" +hpet_ram_write_tn_cmp(uint8_t reg_off) "hpet_ram_writel HPET_TN_CMP + %" PRIu8 +hpet_ram_write_invalid(void) "invalid hpet_ram_writel" +hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HPET enabled!" +hpet_ram_write_counter_written(uint8_t reg_off, uint64_t value, uint64_t counter) "HPET counter + %" PRIu8 "written. crt = 0x%" PRIx64 " -> 0x%" PRIx64 |