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| author | Atish Patra <atish.patra@wdc.com> | 2022-06-20 16:15:52 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | a5a92fd6ef038170231933c60cc2780f52b3a2e1 (patch) | |
| tree | 9bc5c4429818ee21e9f8cbe4954f6d5b1a0b04e0 /hw/timer/avr_timer16.c | |
| parent | 562009e47c622298f82ee7557be9e15d5e50cee5 (diff) | |
| download | qemu-a5a92fd6ef038170231933c60cc2780f52b3a2e1.zip qemu-a5a92fd6ef038170231933c60cc2780f52b3a2e1.tar.gz qemu-a5a92fd6ef038170231933c60cc2780f52b3a2e1.tar.bz2 | |
target/riscv: Implement PMU CSR predicate function for S-mode
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/timer/avr_timer16.c')
0 files changed, 0 insertions, 0 deletions