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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2024-11-14 17:48:38 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-01-27 09:38:15 +0100 |
| commit | 134d9e5c0c4ae2fe64817a185730ec8b7835d573 (patch) | |
| tree | dee7d5d95eee454fc5e697dcc1d058b48f901764 /hw/timer/aspeed_timer.c | |
| parent | 8a139ae719616d85d835528a35f41eb23bfa54c7 (diff) | |
| download | qemu-134d9e5c0c4ae2fe64817a185730ec8b7835d573.zip qemu-134d9e5c0c4ae2fe64817a185730ec8b7835d573.tar.gz qemu-134d9e5c0c4ae2fe64817a185730ec8b7835d573.tar.bz2 | |
hw/sd/sdhci: Introduce a new Write Protected pin inverted property
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some boards are
design Write Protected pin active high. In other words, write enable the bit 19
should be 0 and write protected the bit 19 should be 1 at the
Present State Register (0x24). To support it, introduces a new "wp-inverted"
property and set it false by default.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20241114094839.4128404-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw/timer/aspeed_timer.c')
0 files changed, 0 insertions, 0 deletions