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| author | Eduardo Habkost <ehabkost@redhat.com> | 2018-01-09 13:45:17 -0200 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-01-17 23:04:31 -0200 |
| commit | ac96c41354b7e4c70b756342d9b686e31ab87458 (patch) | |
| tree | c64ca3c113a2bec3ea2c523c78c04b248a877fd7 /hw/timer/arm_mptimer.c | |
| parent | 1b3420e1c4d523c49866cca4e7544753201cd43d (diff) | |
| download | qemu-ac96c41354b7e4c70b756342d9b686e31ab87458.zip qemu-ac96c41354b7e4c70b756342d9b686e31ab87458.tar.gz qemu-ac96c41354b7e4c70b756342d9b686e31ab87458.tar.bz2 | |
i386: Add new -IBRS versions of Intel CPU models
The new MSR IA32_SPEC_CTRL MSR was introduced by a recent Intel
microcode updated and can be used by OSes to mitigate
CVE-2017-5715. Unfortunately we can't change the existing CPU
models without breaking existing setups, so users need to
explicitly update their VM configuration to use the new *-IBRS
CPU model if they want to expose IBRS to guests.
The new CPU models are simple copies of the existing CPU models,
with just CPUID_7_0_EDX_SPEC_CTRL added and model_id updated.
Cc: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20180109154519.25634-6-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw/timer/arm_mptimer.c')
0 files changed, 0 insertions, 0 deletions