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| author | Chalapathi V <chalapathi.v@linux.ibm.com> | 2024-06-26 04:05:24 -0500 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-07-26 09:21:06 +1000 |
| commit | 29318db133d0b2523bda771f76aa50c08842527f (patch) | |
| tree | ad5bf163e488867107d16fa19f2a793143ae3f27 /hw/ssi/trace-events | |
| parent | 117664a1e70e6adff1e4384702a9d8343597b5b9 (diff) | |
| download | qemu-29318db133d0b2523bda771f76aa50c08842527f.zip qemu-29318db133d0b2523bda771f76aa50c08842527f.tar.gz qemu-29318db133d0b2523bda771f76aa50c08842527f.tar.bz2 | |
hw/ssi: Add SPI model
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI configuration component is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
Reviewed-by: Caleb Schlossin <calebs@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
[np: Fix FDT macro compile for qtest]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'hw/ssi/trace-events')
| -rw-r--r-- | hw/ssi/trace-events | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index 7b5ad6a..2cc29e1 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -32,3 +32,9 @@ ibex_spi_host_reset(const char *msg) "%s" ibex_spi_host_transfer(uint32_t tx_data, uint32_t rx_data) "tx_data: 0x%" PRIx32 " rx_data: @0x%" PRIx32 ibex_spi_host_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 ibex_spi_host_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size %u:" + +#pnv_spi.c +pnv_spi_read(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " val 0x%" PRIx64 +pnv_spi_write(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " val 0x%" PRIx64 +pnv_spi_read_RDR(uint64_t val) "data extracted = 0x%" PRIx64 +pnv_spi_write_TDR(uint64_t val) "being written, data written = 0x%" PRIx64 |