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| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-09 23:53:45 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-09 23:59:12 +0100 |
| commit | c0f809c46aa271f29a9e6268cdeda1f21301a8ef (patch) | |
| tree | 01dcf7fa000ec9d9b73610a7d3a6599b198ace1f /hw/sh7750.c | |
| parent | 759c90ba3d4f8dcb748d7719f7ea82b181ffd590 (diff) | |
| download | qemu-c0f809c46aa271f29a9e6268cdeda1f21301a8ef.zip qemu-c0f809c46aa271f29a9e6268cdeda1f21301a8ef.tar.gz qemu-c0f809c46aa271f29a9e6268cdeda1f21301a8ef.tar.bz2 | |
target-sh4: implement writes to mmaped ITLB
Some Linux kernels seems to implement ITLB/UTLB flushing through by
writing all TLB entries through the memory mapped interface instead
of writing one to MMUCR.TI.
Implement memory mapped ITLB write interface so that such kernels can
boot. This fixes https://bugs.launchpad.net/bugs/700774 .
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'hw/sh7750.c')
| -rw-r--r-- | hw/sh7750.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/sh7750.c b/hw/sh7750.c index 9e54ad1..36b702f 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -670,6 +670,8 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, /* do nothing */ break; case MM_ITLB_ADDR: + cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); + break; case MM_ITLB_DATA: /* XXXXX */ abort(); |