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author | Peter Maydell <peter.maydell@linaro.org> | 2023-06-06 11:46:08 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2023-06-19 11:24:21 +0100 |
commit | f837b468cdaa7e736b5385c7dc4f8c5adcad3bf1 (patch) | |
tree | 3bb73be0e6e4c0bdeac4a104e53138a72c222d5b /hw/sd | |
parent | 946ccfd590f65c09211c4899446e07ef589bc093 (diff) | |
download | qemu-f837b468cdaa7e736b5385c7dc4f8c5adcad3bf1.zip qemu-f837b468cdaa7e736b5385c7dc4f8c5adcad3bf1.tar.gz qemu-f837b468cdaa7e736b5385c7dc4f8c5adcad3bf1.tar.bz2 |
hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1
In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner
A10 PIC model; however in the process we introduced a regression.
This is because the old code was robust against the incoming 'level'
argument being something other than 0 or 1, whereas the new code was
not.
In particular, the allwinner-sdhost code treats its IRQ line
as 0-vs-non-0 rather than 0-vs-1, so when the SD controller
set its IRQ line for any reason other than transmit the
interrupt controller would ignore it. The observed effect
was a guest timeout when rebooting the guest kernel.
Handle level values other than 0 or 1, to restore the old
behaviour.
Fixes: 2c5fa0778c3b430 ("hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()")
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20230606104609.3692557-2-peter.maydell@linaro.org
Diffstat (limited to 'hw/sd')
0 files changed, 0 insertions, 0 deletions