diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2018-02-08 13:48:07 -0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2018-02-13 16:15:08 +0100 |
| commit | ea55a221bfc04bde7c7874ecd98881e09763a192 (patch) | |
| tree | ea7a678431415aea7fc4c93e9ca335636995095e /hw/sd/sdhci-internal.h | |
| parent | 06c5120b094700d21d36eb5db00f7bb60ea65868 (diff) | |
| download | qemu-ea55a221bfc04bde7c7874ecd98881e09763a192.zip qemu-ea55a221bfc04bde7c7874ecd98881e09763a192.tar.gz qemu-ea55a221bfc04bde7c7874ecd98881e09763a192.tar.bz2 | |
sdhci: implement the Host Control 2 register (tuning sequence)
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
from qemu/xilinx tag xilinx-v2015.2]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-Id: <20180208164818.7961-20-f4bug@amsat.org>
Diffstat (limited to 'hw/sd/sdhci-internal.h')
| -rw-r--r-- | hw/sd/sdhci-internal.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 9ab1a71..b3f2692 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -188,6 +188,16 @@ FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1); FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1); FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1); +/* Host Control Register 2 (since v3) */ +#define SDHC_HOSTCTL2 0x3E +FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3); +FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); +FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); + /* HWInit Capabilities Register 0x05E80080 */ #define SDHC_CAPAB 0x40 FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); |