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| author | Atish Patra <atishp@rivosinc.com> | 2022-06-20 16:15:54 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | 18d6d89efc60f1c030c4a8a22816d2d911ece105 (patch) | |
| tree | 7b54fb208e2e56e5085f1219a1ad86c01aa0f9dd /hw/sd/sd.c | |
| parent | d3be1299fb37e50535438a675a5b02f5bc068c14 (diff) | |
| download | qemu-18d6d89efc60f1c030c4a8a22816d2d911ece105.zip qemu-18d6d89efc60f1c030c4a8a22816d2d911ece105.tar.gz qemu-18d6d89efc60f1c030c4a8a22816d2d911ece105.tar.bz2 | |
target/riscv: pmu: Make number of counters configurable
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented by the cpu.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-5-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/sd/sd.c')
0 files changed, 0 insertions, 0 deletions