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| author | Keith Packard <keithp@keithp.com> | 2020-01-28 15:32:16 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-10 12:01:36 -0800 |
| commit | ae4a70c07196b76a67b772318b714ce910e10004 (patch) | |
| tree | 39c8bb3422238299146a5d480d57a98cf0a69021 /hw/rtc | |
| parent | 0e404da00737eaa69204e7f3446b85b57d397e4a (diff) | |
| download | qemu-ae4a70c07196b76a67b772318b714ce910e10004.zip qemu-ae4a70c07196b76a67b772318b714ce910e10004.tar.gz qemu-ae4a70c07196b76a67b772318b714ce910e10004.tar.bz2 | |
riscv: Separate FPU register size from core register size in gdbstub [v2]
The size of the FPU registers is dictated by the 'f' and 'd' features,
not the core processor register size. Processors with the 'd' feature
have 64-bit FPU registers. Processors without the 'd' feature but with
the 'f' feature have 32-bit FPU registers.
Signed-off-by: Keith Packard <keithp@keithp.com>
[Palmer: This requires manually triggering a rebuild of
riscv32-softmmu/gdbstub-xml.c]
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'hw/rtc')
0 files changed, 0 insertions, 0 deletions