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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2024-11-04 09:38:38 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-11-07 08:18:17 +1000 |
| commit | cd5d265f42fbb1d29cbc9d8805821149101c1d23 (patch) | |
| tree | 4e7109e8d475ae3e27079f867e126fa22d90e1c8 /hw/riscv | |
| parent | b069018e2fe1fc613f5eeecc810050210e845528 (diff) | |
| download | qemu-cd5d265f42fbb1d29cbc9d8805821149101c1d23.zip qemu-cd5d265f42fbb1d29cbc9d8805821149101c1d23.tar.gz qemu-cd5d265f42fbb1d29cbc9d8805821149101c1d23.tar.bz2 | |
hw/riscv/riscv-iommu: change 'depth' to int
Coverity reports an unsigned overflow when doing:
for (; depth-- > 0; ) {
When depth = 0 inside riscv_iommu_ctx_fetch().
Building it with a recent GCC the code doesn't actually break with depth
= 0, i.e. the comparison "0-- > 0" will exit the loop instead of
proceeding, but 'depth' will retain the overflow value afterwards.
This behavior can be compiler dependent, so change 'depth' to int to
remove this potential ambiguity.
Resolves: Coverity CID 1564783
Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241104123839.533442-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/riscv-iommu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 12f01a7..164a716 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -863,7 +863,7 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx) /* Device Context format: 0: extended (64 bytes) | 1: base (32 bytes) */ const int dc_fmt = !s->enable_msi; const size_t dc_len = sizeof(dc) >> dc_fmt; - unsigned depth; + int depth; uint64_t de; switch (mode) { |