diff options
| author | yang.zhang <yang.zhang@hexintek.com> | 2023-07-07 11:23:06 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-07-10 22:29:15 +1000 |
| commit | c5cc248b478bc21e50845ba6b2414c4a688e195f (patch) | |
| tree | 446e7ba209b478a4f4a2cc7516d6312802748451 /hw/riscv | |
| parent | 32b2d75bf7fab6fa82dd01b2413ca14753b90973 (diff) | |
| download | qemu-c5cc248b478bc21e50845ba6b2414c4a688e195f.zip qemu-c5cc248b478bc21e50845ba6b2414c4a688e195f.tar.gz qemu-c5cc248b478bc21e50845ba6b2414c4a688e195f.tar.bz2 | |
target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly
Should set/get riscv all reg timer,i.e, time/compare/frequency/state.
Signed-off-by: Yang Zhang <yang.zhang@hexintek.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230707032306.4606-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
0 files changed, 0 insertions, 0 deletions