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| author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2024-02-03 19:11:09 +0900 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
| commit | 742cc269c7e67352ebeecc528b0ade547a24de72 (patch) | |
| tree | 7c51bf47a993704e53229e47f92ed4f2a7543c7a /hw/riscv | |
| parent | 0e350c1adab597ecb194a0c091c2180deed96d59 (diff) | |
| download | qemu-742cc269c7e67352ebeecc528b0ade547a24de72.zip qemu-742cc269c7e67352ebeecc528b0ade547a24de72.tar.gz qemu-742cc269c7e67352ebeecc528b0ade547a24de72.tar.bz2 | |
target/riscv: Move misa_mxl_max to class
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240203-riscv-v11-2-a23f4848a628@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/boot.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05..12f9792 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,8 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return harts->harts[0].env.misa_mxl_max == MXL_RV32; + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); + return mcc->misa_mxl_max == MXL_RV32; } /* |