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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-06-17 09:25:36 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-23 11:39:47 +0100 |
| commit | 58f7f3c4526ce90accc87006531e12971a366f67 (patch) | |
| tree | fa1bdbc53bc044b4ff0756dcbcee306465fad9e1 /hw/riscv | |
| parent | adbb23b6a88341fa66a8cfaebedeeadd9a7ac891 (diff) | |
| download | qemu-58f7f3c4526ce90accc87006531e12971a366f67.zip qemu-58f7f3c4526ce90accc87006531e12971a366f67.tar.gz qemu-58f7f3c4526ce90accc87006531e12971a366f67.tar.bz2 | |
hw/arm/mps2: Add SPI devices
From 'Application Note AN385', chapter 3.9, SPI:
The SMM implements five PL022 SPI modules.
Two pairs of modules share the same OR-gated IRQ.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200617072539.32686-12-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/riscv')
0 files changed, 0 insertions, 0 deletions