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| author | Conor Dooley <conor.dooley@microchip.com> | 2024-01-24 12:55:49 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
| commit | afa42c21b5984bb9846e498bb00b1bdc28f56ab5 (patch) | |
| tree | c6ec73a3fab093425df8fa33226ac179586b7188 /hw/riscv/sifive_u.c | |
| parent | 79b50e2c80e50391b7f06b275fbc11f9a4ee168a (diff) | |
| download | qemu-afa42c21b5984bb9846e498bb00b1bdc28f56ab5.zip qemu-afa42c21b5984bb9846e498bb00b1bdc28f56ab5.tar.gz qemu-afa42c21b5984bb9846e498bb00b1bdc28f56ab5.tar.bz2 | |
target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS
A cpu may not have the same xlen as the compile time target, and
misa_mxl_max is the source of truth for what the hart supports.
The conversion from misa_mxl_max to xlen already has one user, so
introduce a helper and use that to populate the isa string.
Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240124-swear-monthly-56c281f809a6@spud>
[ Changes by AF:
- Convert to use RISCVCPUClass *mcc
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
0 files changed, 0 insertions, 0 deletions