diff options
| author | Anup Patel <anup.patel@wdc.com> | 2021-08-31 16:36:01 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-09-21 07:56:49 +1000 |
| commit | b8fb878aa2485fd41502295f0ff5362a67c8ba68 (patch) | |
| tree | 42250dd651e676117144343ea1d353a1d8ceb6e9 /hw/riscv/shakti_c.c | |
| parent | cc63a18282d8e8cd96d8bf26c29cad2e879ff9f6 (diff) | |
| download | qemu-b8fb878aa2485fd41502295f0ff5362a67c8ba68.zip qemu-b8fb878aa2485fd41502295f0ff5362a67c8ba68.tar.gz qemu-b8fb878aa2485fd41502295f0ff5362a67c8ba68.tar.bz2 | |
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
The RISC-V ACLINT is more modular and backward compatible with
original SiFive CLINT so instead of duplicating the original
SiFive CLINT implementation we upgrade the current SiFive CLINT
implementation to RISC-V ACLINT implementation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210831110603.338681-3-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/shakti_c.c')
| -rw-r--r-- | hw/riscv/shakti_c.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index f9f0a45..2f084d3 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -124,10 +124,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) SHAKTI_C_PLIC_CONTEXT_STRIDE, shakti_c_memmap[SHAKTI_C_PLIC].size); - sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base, - shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, - SIFIVE_CLINT_TIMEBASE_FREQ, false); + riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base, + 0, 1, false); + riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base + + RISCV_ACLINT_SWI_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1, + RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { |