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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-01-15 15:00:27 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-01-16 14:34:46 -0800 |
| commit | a8259b53230782f5e0a0d66013655c4ed5d71b7e (patch) | |
| tree | 682f8a500c9935c88f2f93ac6fd0cf44a7e4e0a1 /hw/riscv/boot.c | |
| parent | 138ca49a82b978f035b709abee45324dd7ab3e68 (diff) | |
| download | qemu-a8259b53230782f5e0a0d66013655c4ed5d71b7e.zip qemu-a8259b53230782f5e0a0d66013655c4ed5d71b7e.tar.gz qemu-a8259b53230782f5e0a0d66013655c4ed5d71b7e.tar.bz2 | |
riscv: Pass RISCVHartArrayState by pointer
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.
Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/boot.c')
| -rw-r--r-- | hw/riscv/boot.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 10a601b..0d38bb7 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -33,14 +33,12 @@ #include <libfdt.h> -bool riscv_is_32bit(RISCVHartArrayState harts) +bool riscv_is_32bit(RISCVHartArrayState *harts) { - RISCVCPU hart = harts.harts[0]; - - return riscv_cpu_is_32bit(&hart.env); + return riscv_cpu_is_32bit(&harts->harts[0].env); } -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr) { if (riscv_is_32bit(harts)) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); @@ -247,7 +245,7 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, &address_space_memory); } -void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr start_addr, hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, |