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| author | Alexander Graf <agraf@suse.de> | 2012-06-20 21:27:02 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-06-24 01:04:52 +0200 |
| commit | 2a7a47fc6c19703a849a34243701a09052cb1bc6 (patch) | |
| tree | b7206463004047ffd2d1349c0c4c4ea7831d3f7c /hw/ppce500_mpc8544ds.c | |
| parent | e42a61f185f859246c14445b6e98e195eb3b977b (diff) | |
| download | qemu-2a7a47fc6c19703a849a34243701a09052cb1bc6.zip qemu-2a7a47fc6c19703a849a34243701a09052cb1bc6.tar.gz qemu-2a7a47fc6c19703a849a34243701a09052cb1bc6.tar.bz2 | |
PPC: BookE: Implement EPR SPR
On the e500 series, accessing SPR_EPR magically turns into an access at
that CPU's IACK register on the MPIC. Implement that logic to get kernels
that make use of that feature work.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/ppce500_mpc8544ds.c')
| -rw-r--r-- | hw/ppce500_mpc8544ds.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index d38ad99..8b9fd83 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -469,6 +469,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; + env->mpic_cpu_base = MPC8544_MPIC_REGS_BASE + 0x20000; ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); |