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| author | David Gibson <david@gibson.dropbear.id.au> | 2017-05-09 15:03:12 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-05-11 09:45:15 +1000 |
| commit | 9bf502fe127f04e393cacae9f2666e0c98c6df4f (patch) | |
| tree | 467d9ccc75073e4fb10936dac0b084ecf0b0659a /hw/ppc | |
| parent | 5c6b487d673f1f5e5a30f6168bad3bc5cef40180 (diff) | |
| download | qemu-9bf502fe127f04e393cacae9f2666e0c98c6df4f.zip qemu-9bf502fe127f04e393cacae9f2666e0c98c6df4f.tar.gz qemu-9bf502fe127f04e393cacae9f2666e0c98c6df4f.tar.bz2 | |
spapr: Don't accidentally advertise HTM support on POWER9
Logic in spapr_populate_pa_features() enables the bit advertising
Hardware Transactional Memory (HTM) in the guest's device tree only when
KVM advertises its availability with the KVM_CAP_PPC_HTM feature.
However, this assumes that the HTM bit is off in the base template used for
the device tree value. That is true for POWER8, but not for POWER9.
It looks like that was accidentally changed in 9fb4541 "spapr: Enable ISA
3.0 MMU mode selection via CAS".
Fixes: 9fb4541f5803f8d2ba116b12113386e26482ba30
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/spapr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e2dc77c..1b7cada 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -219,7 +219,7 @@ static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, /* 16: Vector */ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ |