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| author | Alexander Graf <agraf@suse.de> | 2013-01-04 11:21:04 +0100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-01-07 17:37:11 +0100 |
| commit | 68c2dd70068fe82a1989d0d5b70a1ab400bde19a (patch) | |
| tree | e9be2de2931bf374beb4914b33f214d31dfec0c2 /hw/ppc | |
| parent | 1a61a9ae61cdf7b7d24c3eb711fe772c196c235e (diff) | |
| download | qemu-68c2dd70068fe82a1989d0d5b70a1ab400bde19a.zip qemu-68c2dd70068fe82a1989d0d5b70a1ab400bde19a.tar.gz qemu-68c2dd70068fe82a1989d0d5b70a1ab400bde19a.tar.bz2 | |
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,
but only implemented it halfway correctly.
This patch adds support for
* dynamic enablement of the EPR facility
* interrupt acknowledgement only when the interrupt is delivered
This way the implementation now is closer to real hardware.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/e500.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 5d70618..3a9e1c7 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -497,8 +497,8 @@ void ppce500_init(PPCE500Params *params) irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; - env->mpic_cpu_base = MPC8544_CCSRBAR_BASE + - MPC8544_MPIC_REGS_OFFSET + 0x20000; + env->mpic_iack = MPC8544_CCSRBAR_BASE + + MPC8544_MPIC_REGS_OFFSET + 0x200A0; ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); |