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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-06-14 00:16:23 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-03-13 02:47:04 +1000 |
| commit | 5e97fd48d7c5429ec9ec83b7f7169462d4a9d2e8 (patch) | |
| tree | be215b601077ed2fd7da94de5e958d8b0ec9c087 /hw/ppc | |
| parent | 678b6f1af75ef42f510495a81fe8562e872e9daf (diff) | |
| download | qemu-5e97fd48d7c5429ec9ec83b7f7169462d4a9d2e8.zip qemu-5e97fd48d7c5429ec9ec83b7f7169462d4a9d2e8.tar.gz qemu-5e97fd48d7c5429ec9ec83b7f7169462d4a9d2e8.tar.bz2 | |
spapr: set MSR[ME] and MSR[FP] on client entry
The initial MSR state for the OpenFirmware binding specifies
MSR[ME] and MSR[FP] are set.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/spapr_cpu_core.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 40b7c52..58cb992 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -39,9 +39,13 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) /* * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state - * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values". + * as 32bit (MSR_SF=0) with MSR_ME=1 and MSR_FP=1 in "8.2.1. Initial + * Register Values". This can also be found in "LoPAPR 1.1" "C.9.2.1 + * Initial Register Values". */ env->msr &= ~(1ULL << MSR_SF); + env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP); + env->spr[SPR_HIOR] = 0; lpcr = env->spr[SPR_LPCR]; |