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| author | Cédric Le Goater <clg@kaod.org> | 2022-08-17 17:08:29 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-08-31 14:08:06 -0300 |
| commit | da116a8aab47695a8364708f2e1d14ed6fcc659f (patch) | |
| tree | 9d8b3fc8e9f78a7689c2ec4b01a9d3be30d82daa /hw/ppc/ppc405.h | |
| parent | 695bce07dc1c0f7de054fb471a494d572e649e07 (diff) | |
| download | qemu-da116a8aab47695a8364708f2e1d14ed6fcc659f.zip qemu-da116a8aab47695a8364708f2e1d14ed6fcc659f.tar.gz qemu-da116a8aab47695a8364708f2e1d14ed6fcc659f.tar.bz2 | |
ppc/ppc405: QOM'ify MAL
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <d54a243dff94d95ba30dbcc09c27700a90ade932.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/ppc405.h')
| -rw-r--r-- | hw/ppc/ppc405.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index cb34792..31c94e4 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -244,6 +244,7 @@ struct Ppc405SoCState { Ppc405OpbaState opba; Ppc405PobState pob; Ppc405PlbState plb; + Ppc4xxMalState mal; }; /* PowerPC 405 core */ |