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authorAvi Kivity <avi@redhat.com>2011-07-24 17:47:18 +0300
committerAvi Kivity <avi@redhat.com>2011-08-24 20:17:39 +0300
commitd2c33733c85c4df7cd0f5e0426a22e737d542516 (patch)
treedaa4228405f900b9189b946225b61e7346bb74a3 /hw/pci_host.c
parentbe35694da941168603b09a7420bcc476d745fc41 (diff)
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pci_host: convert conf index and data ports to memory API
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'hw/pci_host.c')
-rw-r--r--hw/pci_host.c86
1 files changed, 38 insertions, 48 deletions
diff --git a/hw/pci_host.c b/hw/pci_host.c
index 2e8a29f..44c6c20 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -94,82 +94,72 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
+ PCIHostState *s = opaque;
- PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
+ PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
__func__, addr, len, val);
s->config_reg = val;
}
-static uint32_t pci_host_config_read(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
+ PCIHostState *s = opaque;
uint32_t val = s->config_reg;
- PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
+ PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
-static void pci_host_data_write(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, data_handler);
- PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
- addr, len, val);
+ PCIHostState *s = opaque;
+ PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n",
+ addr, len, (unsigned)val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_data_read(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint64_t pci_host_data_read(void *opaque,
+ target_phys_addr_t addr, unsigned len)
{
- PCIHostState *s = container_of(handler, PCIHostState, data_handler);
+ PCIHostState *s = opaque;
uint32_t val;
if (!(s->config_reg & (1 << 31)))
return 0xffffffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
- PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
+ PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
addr, len, val);
return val;
}
-static void pci_host_init(PCIHostState *s)
-{
- s->conf_handler.write = pci_host_config_write;
- s->conf_handler.read = pci_host_config_read;
- s->data_handler.write = pci_host_data_write;
- s->data_handler.read = pci_host_data_read;
-}
+const MemoryRegionOps pci_host_conf_le_ops = {
+ .read = pci_host_config_read,
+ .write = pci_host_config_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
-int pci_host_conf_register_mmio(PCIHostState *s, int endian)
-{
- pci_host_init(s);
- return cpu_register_io_memory_simple(&s->conf_handler, endian);
-}
+const MemoryRegionOps pci_host_conf_be_ops = {
+ .read = pci_host_config_read,
+ .write = pci_host_config_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
-void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
-{
- pci_host_init(s);
- register_ioport_simple(&s->conf_handler, ioport, 4, 4);
- sysbus_init_ioports(&s->busdev, ioport, 4);
-}
+const MemoryRegionOps pci_host_data_le_ops = {
+ .read = pci_host_data_read,
+ .write = pci_host_data_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+const MemoryRegionOps pci_host_data_be_ops = {
+ .read = pci_host_data_read,
+ .write = pci_host_data_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
-int pci_host_data_register_mmio(PCIHostState *s, int endian)
-{
- pci_host_init(s);
- return cpu_register_io_memory_simple(&s->data_handler, endian);
-}
-void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
-{
- pci_host_init(s);
- register_ioport_simple(&s->data_handler, ioport, 4, 1);
- register_ioport_simple(&s->data_handler, ioport, 4, 2);
- register_ioport_simple(&s->data_handler, ioport, 4, 4);
- sysbus_init_ioports(&s->busdev, ioport, 4);
-}