aboutsummaryrefslogtreecommitdiff
path: root/hw/pci-bridge
diff options
context:
space:
mode:
authorJonathan Cameron <Jonathan.Cameron@huawei.com>2024-09-16 18:35:13 +0100
committerMichael S. Tsirkin <mst@redhat.com>2024-11-04 16:03:24 -0500
commit1478b5609022ed4331bff83d06cefed983df82ac (patch)
treeb001f92c4b088c485753ce3f811787512ec6365d /hw/pci-bridge
parentdf37d496981344c24746be3553d7f6d8a0a9b1b9 (diff)
downloadqemu-1478b5609022ed4331bff83d06cefed983df82ac.zip
qemu-1478b5609022ed4331bff83d06cefed983df82ac.tar.gz
qemu-1478b5609022ed4331bff83d06cefed983df82ac.tar.bz2
hw/pci-bridge/cxl_root_port: Provide x-speed and x-width properties.
Approach copied from gen_pcie_root_port.c Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting it's maximum values. The actual value after 'training' will depend on the downstream device configuration. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916173518.1843023-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Fan Ni <fan.ni@samsung.com>
Diffstat (limited to 'hw/pci-bridge')
-rw-r--r--hw/pci-bridge/cxl_root_port.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 2dd1023..5e2156d 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -24,6 +24,7 @@
#include "hw/pci/pcie_port.h"
#include "hw/pci/msi.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
#include "hw/cxl/cxl.h"
@@ -206,6 +207,10 @@ static Property gen_rp_props[] = {
-1),
DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64,
-1),
+ DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
+ speed, PCIE_LINK_SPEED_64),
+ DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
+ width, PCIE_LINK_WIDTH_32),
DEFINE_PROP_END_OF_LIST()
};