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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-11-25 11:52:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-12-16 15:59:07 +0000 |
| commit | f4c636b0c2f53531e16e018b6e096d26b5809dfd (patch) | |
| tree | a86b9f51dbfb78190e0531b92f9c01e8c7cbc401 /hw/pci-bridge | |
| parent | bb27210c8cb8c246b221dad178a3e04566d38e3d (diff) | |
| download | qemu-f4c636b0c2f53531e16e018b6e096d26b5809dfd.zip qemu-f4c636b0c2f53531e16e018b6e096d26b5809dfd.tar.gz qemu-f4c636b0c2f53531e16e018b6e096d26b5809dfd.tar.bz2 | |
pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset
Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to
3-phase reset, so they don't need to use the deprecated
device_class_set_parent_reset() function any more.
We have to do both in the same commit, because they keep the
parent_reset field in their common parent class's class struct.
Note that pnv_phb_root_port_class_init() was pointlessly setting
dc->reset twice, once by calling device_class_set_parent_reset()
and once directly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221125115240.3005559-5-peter.maydell@linaro.org
Diffstat (limited to 'hw/pci-bridge')
| -rw-r--r-- | hw/pci-bridge/cxl_root_port.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index fb213fa..6664783 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -138,12 +138,14 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) component_bar); } -static void cxl_rp_reset(DeviceState *dev) +static void cxl_rp_reset_hold(Object *obj) { - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); - CXLRootPort *crp = CXL_ROOT_PORT(dev); + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); + CXLRootPort *crp = CXL_ROOT_PORT(obj); - rpc->parent_reset(dev); + if (rpc->parent_phases.hold) { + rpc->parent_phases.hold(obj); + } latch_registers(crp); } @@ -199,6 +201,7 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PCIDeviceClass *k = PCI_DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc); k->vendor_id = PCI_VENDOR_ID_INTEL; @@ -209,7 +212,8 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data) k->config_write = cxl_rp_write_config; device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize); - device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL, + &rpc->parent_phases); rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET; rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET; |