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author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-29 17:39:17 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2022-07-29 17:39:17 -0700 |
commit | 3916603e0c1d909e14e09d5ebcbdaa9c9e21adf3 (patch) | |
tree | d1d61e002dc917bdc59f8f48b230dc711228b002 /hw/pci-bridge/cxl_root_port.c | |
parent | fc2cc19ffa02c86ec1471ec8fdbc39d33fcec626 (diff) | |
parent | 74725231d6fd1605d8b60c5afc2c0aec2f0b1e67 (diff) | |
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Merge tag 'pull-la-20220729' of https://gitlab.com/rth7680/qemu into staging
Rename ls7a to virt, when it's board not chipset related.
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# gpg: Signature made Fri 29 Jul 2022 05:35:59 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
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# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-la-20220729' of https://gitlab.com/rth7680/qemu:
hw/loongarch: Change macro name 'LS7A_XXX' to 'VIRT_XXX'
hw/loongarch: Rename file 'loongson3.XXX' to 'virt.XXX'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/pci-bridge/cxl_root_port.c')
0 files changed, 0 insertions, 0 deletions