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| author | Scott Wood <scottwood@freescale.com> | 2012-12-21 16:15:39 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-01-07 17:37:09 +0100 |
| commit | e99fd8af63a1692a1159cba8fa4943f2589adf97 (patch) | |
| tree | fc761e23735e982c7c6062355e188f395f8dd8b2 /hw/openpic.c | |
| parent | 4c4f0e4801ac79632d03867c88aafc90b4ce503c (diff) | |
| download | qemu-e99fd8af63a1692a1159cba8fa4943f2589adf97.zip qemu-e99fd8af63a1692a1159cba8fa4943f2589adf97.tar.gz qemu-e99fd8af63a1692a1159cba8fa4943f2589adf97.tar.bz2 | |
openpic: lower interrupt when reading the MSI register
This will stop things from breaking once it's properly treated as a
level-triggered interrupt. Note that it's the MPIC's MSI cascade
interrupts that are level-triggered; the individual MSIs are
edge-triggered.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/openpic.c')
| -rw-r--r-- | hw/openpic.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/openpic.c b/hw/openpic.c index 9243e70..f4df66d 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -810,6 +810,7 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) r = opp->msi[srs].msir; /* Clear on read */ opp->msi[srs].msir = 0; + openpic_set_irq(opp, opp->irq_msi + srs, 0); break; case 0x120: /* MSISR */ for (i = 0; i < MAX_MSI; i++) { |