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| author | Alexander Graf <agraf@suse.de> | 2013-12-17 19:42:34 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:34 +0000 |
| commit | 832ffa1ce073f010fd1c766361b2e35ce3f105d3 (patch) | |
| tree | d1ee95fe5c5699ec01f71537b1b649f296a4a42c /hw/net | |
| parent | e952d8c77a59dd31b5a4332f19e19f43dc90bd68 (diff) | |
| download | qemu-832ffa1ce073f010fd1c766361b2e35ce3f105d3.zip qemu-832ffa1ce073f010fd1c766361b2e35ce3f105d3.tar.gz qemu-832ffa1ce073f010fd1c766361b2e35ce3f105d3.tar.bz2 | |
target-arm: A64: add support for logical (shifted register)
Add support for the instructions described in "C3.5.10 Logical
(shifted register)".
We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems
a better tradeoff than having to rework the whole 32 bit decoder
and also make 32 bit result calculation in A64 awkward.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: some refactoring to avoid hidden allocation of temps,
rework flags, use enums for shift types,
renaming of functions]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
[PMM: Use TCG's andc/orc/eqv ops rather than manually inverting]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'hw/net')
0 files changed, 0 insertions, 0 deletions