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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-11 17:44:53 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-13 17:16:04 +0100 |
| commit | 0bd0ba87a0fa22b5d3dda206f1920547df6eb918 (patch) | |
| tree | 1fe5807f61584844c5da97813c581f30d9eb18b2 /hw/net/virtio-net.c | |
| parent | a34606dbb3c7094b6e9fde5e1463a306b6921255 (diff) | |
| download | qemu-0bd0ba87a0fa22b5d3dda206f1920547df6eb918.zip qemu-0bd0ba87a0fa22b5d3dda206f1920547df6eb918.tar.gz qemu-0bd0ba87a0fa22b5d3dda206f1920547df6eb918.tar.bz2 | |
hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region
Rather than using I/O registers for RAM buffer, having to
swap endianness back and forth (because the core memory layer
automatically swaps endiannes for us), declare the buffers
as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have
any more I/O regions. Remove the now unused s->regs[] array.
The memory flat view becomes:
FlatView #0
Root memory region: system
0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf
00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio
00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io
0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf
0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io
0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf
00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io
0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf
0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20241114210010.34502-18-philmd@linaro.org>
Diffstat (limited to 'hw/net/virtio-net.c')
0 files changed, 0 insertions, 0 deletions