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| author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2023-06-02 16:25:16 +0900 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2023-07-07 16:35:12 +0800 |
| commit | e414270000e9f7fe2a56d314ab85259aeaf1bd91 (patch) | |
| tree | 28e8ad362081c7787f081c46184bed46111c94bc /hw/net/trace-events | |
| parent | b6aeee02980e193f744f74c48fd900940feb2799 (diff) | |
| download | qemu-e414270000e9f7fe2a56d314ab85259aeaf1bd91.zip qemu-e414270000e9f7fe2a56d314ab85259aeaf1bd91.tar.gz qemu-e414270000e9f7fe2a56d314ab85259aeaf1bd91.tar.bz2 | |
e1000e: Add ICR clearing by corresponding IMS bit
The datasheet does not say what happens when interrupt was asserted
(ICR.INT_ASSERT=1) and auto mask is *not* active.
However, section of 13.3.27 the PCIe* GbE Controllers Open Source
Software Developer’s Manual, which were written for older devices,
namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI &
82573E/82573V/82573L, does say:
> If IMS = 0b, then the ICR register is always clear-on-read. If IMS is
> not 0b, but some ICR bit is set where the corresponding IMS bit is not
> set, then a read does not clear the ICR register. For example, if
> IMS = 10101010b and ICR = 01010101b, then a read to the ICR register
> does not clear it. If IMS = 10101010b and ICR = 0101011b, then a read
> to the ICR register clears it entirely (ICR.INT_ASSERTED = 1b).
Linux does no longer activate auto mask since commit
0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware clears
ICR even in such a case so we also should do so.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'hw/net/trace-events')
| -rw-r--r-- | hw/net/trace-events | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/net/trace-events b/hw/net/trace-events index e4a98b2..3eeacc5 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -217,6 +217,7 @@ e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" e1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to non MSI-X int" e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS" e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" +e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims) "Clearing ICR on read due corresponding IMS bit: 0x%x & 0x%x" e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x" |