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| author | Hao Wu <wuhaotsh@google.com> | 2025-02-19 10:46:05 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-20 15:22:22 +0000 |
| commit | 3d107d36f99c6eec8c8b3cb6bc387b0fcc69d7d9 (patch) | |
| tree | 6ca2317c4080242beb63c4ecb04744f59f3edd1a /hw/net/trace-events | |
| parent | 4e67d50deaf3132f392266e7251cf7ce17be8fa4 (diff) | |
| download | qemu-3d107d36f99c6eec8c8b3cb6bc387b0fcc69d7d9.zip qemu-3d107d36f99c6eec8c8b3cb6bc387b0fcc69d7d9.tar.gz qemu-3d107d36f99c6eec8c8b3cb6bc387b0fcc69d7d9.tar.bz2 | |
hw/net: Add NPCM8XX PCS Module
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250219184609.1839281-15-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/net/trace-events')
| -rw-r--r-- | hw/net/trace-events | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/net/trace-events b/hw/net/trace-events index c35bfb2..72b69c4 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -483,8 +483,8 @@ npcm_gmac_packet_tx_desc_data(const char* name, uint32_t tdes0, uint32_t tdes1) npcm_gmac_tx_desc_owner(const char* name, uint32_t desc_addr) "%s: TX Descriptor @0x%04" PRIX32 " is owned by software" # npcm_pcs.c -npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 -npcm_pcs_reg_write(const char *name, uint16_t indirect_access_baes, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 +npcm_pcs_reg_read(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 +npcm_pcs_reg_write(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 # dp8398x.c dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x" |