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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-09-01 16:40:59 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-14 14:23:19 +0100 |
| commit | 9d8e61918f2ecb67885d90ea5c6ad8e3d73e7db4 (patch) | |
| tree | b1433a02a666573d02b791afeac32749c62690fc /hw/misc | |
| parent | 7b56d1f4aebf25d81d7b73fe1e2aac2d66b8c0ce (diff) | |
| download | qemu-9d8e61918f2ecb67885d90ea5c6ad8e3d73e7db4.zip qemu-9d8e61918f2ecb67885d90ea5c6ad8e3d73e7db4.tar.gz qemu-9d8e61918f2ecb67885d90ea5c6ad8e3d73e7db4.tar.bz2 | |
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
This model implementation is designed for 32-bit accesses.
We can simplify setting the MemoryRegionOps::impl min/max
fields to 32-bit (memory::access_with_adjusted_size() will
take care of the 8/16-bit accesses).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc')
| -rw-r--r-- | hw/misc/a9scu.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c index 3f3dcc4..47f9483 100644 --- a/hw/misc/a9scu.c +++ b/hw/misc/a9scu.c @@ -28,12 +28,6 @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset, return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); case 0x08: /* CPU Power Status */ return s->status; - case 0x09: /* CPU status. */ - return s->status >> 8; - case 0x0a: /* CPU status. */ - return s->status >> 16; - case 0x0b: /* CPU status. */ - return s->status >> 24; case 0x0c: /* Invalidate All Registers In Secure State */ return 0; case 0x40: /* Filtering Start Address Register */ @@ -52,8 +46,6 @@ static void a9_scu_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { A9SCUState *s = (A9SCUState *)opaque; - uint32_t mask = MAKE_64BIT_MASK(0, size * 8); - uint32_t shift; switch (offset) { case 0x00: /* Control */ @@ -62,9 +54,7 @@ static void a9_scu_write(void *opaque, hwaddr offset, case 0x4: /* Configuration: RO */ break; case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ - shift = (offset - 0x8) * 8; - s->status &= ~(mask << shift); - s->status |= ((value & mask) << shift); + s->status = value; break; case 0x0c: /* Invalidate All Registers In Secure State */ /* no-op as we do not implement caches */ @@ -84,6 +74,10 @@ static void a9_scu_write(void *opaque, hwaddr offset, static const MemoryRegionOps a9_scu_ops = { .read = a9_scu_read, .write = a9_scu_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 1, .max_access_size = 4, |