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authorWeiwei Li <liweiwei@iscas.ac.cn>2023-03-27 16:08:50 +0800
committerAlistair Francis <alistair.francis@wdc.com>2023-05-05 10:49:50 +1000
commitfbec3f382af5c1746d7ff803e88daf92175f4c24 (patch)
tree8c7191ecf3b256056a1249f60797c9f3fc15fecb /hw/misc/sifive_u_prci.c
parent2136b6c30c0f0a4653163dd2f72a01a96ad778d2 (diff)
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target/riscv: Remove redundant check on RVH
Check on riscv_cpu_virt_enabled contains the check on RVH. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
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