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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-10-01 09:22:55 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-10-10 14:52:25 +0100 |
| commit | 5b74f9b4ed9033dc5427cd69f5ee37e7b726ecfd (patch) | |
| tree | 44eb39c536742a9b697754dba2f12e5151a628c7 /hw/misc/omap_tap.c | |
| parent | 448e42fdc1013b3497c9a6902f8052488fc8af1a (diff) | |
| download | qemu-5b74f9b4ed9033dc5427cd69f5ee37e7b726ecfd.zip qemu-5b74f9b4ed9033dc5427cd69f5ee37e7b726ecfd.tar.gz qemu-5b74f9b4ed9033dc5427cd69f5ee37e7b726ecfd.tar.bz2 | |
target/arm: Fix cacheattr in get_phys_addr_disabled
Do not apply memattr or shareability for Stage2 translations.
Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
pseudocode in AArch64.S1DisabledOutput.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/omap_tap.c')
0 files changed, 0 insertions, 0 deletions