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author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-03 14:28:15 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-08-24 10:15:11 +0100 |
commit | 8b4c9a50dc9531a729ae4b5941d287ad0422db48 (patch) | |
tree | 41979a56ab5cd289b97744b1babe1b88cefe1399 /hw/misc/mips_cpc.c | |
parent | e60527c5d501e5015a119a0388a27abeae4dac09 (diff) | |
download | qemu-8b4c9a50dc9531a729ae4b5941d287ad0422db48.zip qemu-8b4c9a50dc9531a729ae4b5941d287ad0422db48.tar.gz qemu-8b4c9a50dc9531a729ae4b5941d287ad0422db48.tar.bz2 |
target/arm/translate.c: Delete/amend incorrect comments
In arm_tr_init_disas_context() we have a FIXME comment that suggests
"cpu_M0 can probably be the same as cpu_V0". This isn't in fact
possible: cpu_V0 is used as a temporary inside gen_iwmmxt_shift(),
and that function is called in various places where cpu_M0 contains a
live value (i.e. between gen_op_iwmmxt_movq_M0_wRn() and
gen_op_iwmmxt_movq_wRn_M0() calls). Remove the comment.
We also have a comment on the declarations of cpu_V0/V1/M0 which
claims they're "for efficiency". This isn't true with modern TCG, so
replace this comment with one which notes that they're only used with
the iwmmxt decode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803132815.3861-1-peter.maydell@linaro.org
Diffstat (limited to 'hw/misc/mips_cpc.c')
0 files changed, 0 insertions, 0 deletions