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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2025-02-19 16:44:42 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2025-03-04 14:45:34 +0100
commit543671d9907f7604b83fa9e76cdb04fa9fab9cdc (patch)
tree969e682bbf6a82ec8904fce6abcce6f961670296 /hw/misc/macio
parent3ca8af5445b493ae3bc1520c71de3fd7e4555af4 (diff)
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hw/char/sh_serial: Return correct number of empty RX FIFO elements
In the IOCanReadHandler sh_serial_can_receive(), if the Serial Control Register 'Receive Enable' bit is set (bit 4), then we return a size of (1 << 4) which happens to be equal to 16, so effectively SH_RX_FIFO_LENGTH. The IOReadHandler, sh_serial_receive1() takes care to receive multiple chars, but if the FIFO is partly filled, we only process the number of free slots in the FIFO, discarding the other chars! Fix by returning how many elements the FIFO can queue in the IOCanReadHandler, so we don't have to process more than that in the IOReadHandler, thus not discarding anything. Remove the now unnecessary check on 's->rx_cnt < SH_RX_FIFO_LENGTH' in IOReadHandler, reducing the block indentation. Fixes: 63242a007a1 ("SH4: Serial controller improvement") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-10-philmd@linaro.org>
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