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| author | Alexander Graf <graf@amazon.com> | 2023-06-14 22:56:24 +0000 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-12-30 20:04:50 +0100 |
| commit | ff871d0462d0a7ebdbfadf8c8d6c3726af507f0a (patch) | |
| tree | 13cf1db2aedc993134c9a8ac318bc26408764eab /hw/mips | |
| parent | 7c89e226f878539b633dde3fd9c9f061c34094e3 (diff) | |
| download | qemu-ff871d0462d0a7ebdbfadf8c8d6c3726af507f0a.zip qemu-ff871d0462d0a7ebdbfadf8c8d6c3726af507f0a.tar.gz qemu-ff871d0462d0a7ebdbfadf8c8d6c3726af507f0a.tar.bz2 | |
hw/pci-host/gpex: Allow more than 4 legacy IRQs
Some boards such as vmapple don't do real legacy PCI IRQ swizzling.
Instead, they just keep allocating more board IRQ lines for each new
legacy IRQ. Let's support that mode by giving instantiators a new
"nr_irqs" property they can use to support more than 4 legacy IRQ lines.
In this mode, GPEX will export more IRQ lines, one for each device.
Signed-off-by: Alexander Graf <graf@amazon.com>
Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241223221645.29911-9-phil@philjordan.eu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/mips')
| -rw-r--r-- | hw/mips/loongson3_virt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index f12f8c3..f3cc7a8 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -458,7 +458,7 @@ static inline void loongson3_virt_devices_init(MachineState *machine, virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); - for (i = 0; i < GPEX_NUM_IRQS; i++) { + for (i = 0; i < PCI_NUM_PINS; i++) { irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); |