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author | Marc-André Lureau <marcandre.lureau@redhat.com> | 2022-03-23 19:57:18 +0400 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-04-06 10:50:37 +0200 |
commit | ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec (patch) | |
tree | e44d5190b97904e26b30b974002dcbfd6fbe5c80 /hw/mips | |
parent | e03b56863d2bca3e649e81531c1b0299524481ae (diff) | |
download | qemu-ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec.zip qemu-ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec.tar.gz qemu-ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec.tar.bz2 |
Replace TARGET_WORDS_BIGENDIAN
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done
with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1,
and thus should always be defined to prevent misuse.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Suggested-by: Halil Pasic <pasic@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/mips')
-rw-r--r-- | hw/mips/gt64xxx_pci.c | 6 | ||||
-rw-r--r-- | hw/mips/jazz.c | 2 | ||||
-rw-r--r-- | hw/mips/malta.c | 24 | ||||
-rw-r--r-- | hw/mips/mipssim.c | 2 |
4 files changed, 17 insertions, 17 deletions
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index e0ff1b5..19d0d98 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -986,7 +986,7 @@ static void gt64120_reset(DeviceState *dev) /* FIXME: Malta specific hw assumptions ahead */ /* CPU Configuration */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN s->regs[GT_CPU] = 0x00000000; #else s->regs[GT_CPU] = 0x00001000; @@ -1097,7 +1097,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_TC_CONTROL] = 0x00000000; /* PCI Internal */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN s->regs[GT_PCI0_CMD] = 0x00000000; #else s->regs[GT_PCI0_CMD] = 0x00010001; @@ -1118,7 +1118,7 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN s->regs[GT_PCI1_CMD] = 0x00000000; #else s->regs[GT_PCI1_CMD] = 0x00010001; diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 44f0d48..4d6b44d 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -158,7 +158,7 @@ static void mips_jazz_init(MachineState *machine, [JAZZ_PICA61] = {33333333, 4}, }; -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN big_endian = 1; #else big_endian = 0; diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 6288511..c4474b9 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -367,7 +367,7 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr, /* STATUS Register */ case 0x00208: -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN val = 0x00000012; #else val = 0x00000010; @@ -695,7 +695,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, stw_p(p++, 0xe040); stw_p(p++, 0x0681); /* lui t1, %hi(0xb4000000) */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stw_p(p++, 0xe020); stw_p(p++, 0x0be1); /* lui t0, %hi(0xdf000000) */ @@ -894,7 +894,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, /* Load BAR registers as done by YAMON */ stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */ #else stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */ @@ -903,39 +903,39 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */ #else stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */ #endif stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */ #else stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */ #endif stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */ #else stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */ #endif stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */ #else stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */ #endif stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */ #else stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */ #endif stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */ #else stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */ @@ -1030,7 +1030,7 @@ static uint64_t load_kernel(void) int prom_index = 0; uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr); -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN big_endian = 1; #else big_endian = 0; @@ -1272,7 +1272,7 @@ void mips_malta_init(MachineState *machine) ram_low_postio); } -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN be = 1; #else be = 0; @@ -1353,7 +1353,7 @@ void mips_malta_init(MachineState *machine) * In little endian mode the 32bit words in the bios are swapped, * a neat trick which allows bi-endian firmware. */ -#ifndef TARGET_WORDS_BIGENDIAN +#if !TARGET_BIG_ENDIAN { uint32_t *end, *addr; const size_t swapsize = MIN(bios_size, 0x3e0000); diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index 27a46bd..30bc1c4 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -65,7 +65,7 @@ static uint64_t load_kernel(void) ram_addr_t initrd_offset; int big_endian; -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN big_endian = 1; #else big_endian = 0; |