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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-12-11 18:33:52 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-01-13 09:32:32 +0100 |
| commit | 73be38cbe34df90be4ab9618e62859fa074015ff (patch) | |
| tree | 546197049bbbcdfbced5d0b38cccd2c75095a075 /hw/mips | |
| parent | cf386ca8ab20ecad5efa535f3d48750df740da39 (diff) | |
| download | qemu-73be38cbe34df90be4ab9618e62859fa074015ff.zip qemu-73be38cbe34df90be4ab9618e62859fa074015ff.tar.gz qemu-73be38cbe34df90be4ab9618e62859fa074015ff.tar.bz2 | |
hw/mips/bootloader: Implement nanoMIPS SW opcode generator
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-4-philmd@linaro.org>
Diffstat (limited to 'hw/mips')
| -rw-r--r-- | hw/mips/bootloader.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 0035f37..3e1e733 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -143,9 +143,27 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) bl_gen_i_type(p, 0x0d, rs, rt, imm); } +static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) +{ + uint32_t insn = 0; + + assert(extract32(ofs12, 0, 12) == ofs12); + insn = deposit32(insn, 26, 6, 0b100001); + insn = deposit32(insn, 21, 5, rt); + insn = deposit32(insn, 16, 5, rs); + insn = deposit32(insn, 12, 4, 0b1001); + insn = deposit32(insn, 0, 12, ofs12); + + st_nm32_p(ptr, insn); +} + static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) { - bl_gen_i_type(p, 0x2b, base, rt, offset); + if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + bl_gen_sw_nm(p, rt, base, offset); + } else { + bl_gen_i_type(p, 0x2b, base, rt, offset); + } } static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) |