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authorBenoît Canet <benoit.canet@gmail.com>2011-11-24 14:31:13 +0100
committerAvi Kivity <avi@redhat.com>2011-11-28 15:38:42 +0200
commitaa6e4986b8f6c435bf4e8aa4328b06d9e84524bb (patch)
treed087e4b9001373061fa613655edb511b9197b842 /hw/mcf_uart.c
parent653fa85c9a626f48c92806e4e28c7ccebc05c43e (diff)
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mcf_uart: convert to memory API
Signed-off-by: Benoît Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'hw/mcf_uart.c')
-rw-r--r--hw/mcf_uart.c34
1 files changed, 15 insertions, 19 deletions
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index e6b2ab0..ec6a87f 100644
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -8,8 +8,10 @@
#include "hw.h"
#include "mcf.h"
#include "qemu-char.h"
+#include "exec-memory.h"
typedef struct {
+ MemoryRegion iomem;
uint8_t mr[2];
uint8_t sr;
uint8_t isr;
@@ -64,7 +66,8 @@ static void mcf_uart_update(mcf_uart_state *s)
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
-uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
+uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@@ -182,7 +185,8 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
}
}
-void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
+void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@@ -283,28 +287,20 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
return s;
}
-
-static CPUReadMemoryFunc * const mcf_uart_readfn[] = {
- mcf_uart_read,
- mcf_uart_read,
- mcf_uart_read
-};
-
-static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
- mcf_uart_write,
- mcf_uart_write,
- mcf_uart_write
+static const MemoryRegionOps mcf_uart_ops = {
+ .read = mcf_uart_read,
+ .write = mcf_uart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
+void mcf_uart_mm_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq,
CharDriverState *chr)
{
mcf_uart_state *s;
- int iomemtype;
s = mcf_uart_init(irq, chr);
- iomemtype = cpu_register_io_memory(mcf_uart_readfn,
- mcf_uart_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x40, iomemtype);
+ memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
}