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| author | Bernhard Beschow <shentey@gmail.com> | 2023-02-13 18:30:23 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-02-27 22:29:01 +0100 |
| commit | 29a457cbbc90a9938f8ca3d6bf397e99b9559e58 (patch) | |
| tree | bf732901e4496a8ee20e861ba0632836b8e7c6c2 /hw/isa | |
| parent | c288b6869a033986894607c8412bf23ec93f4d87 (diff) | |
| download | qemu-29a457cbbc90a9938f8ca3d6bf397e99b9559e58.zip qemu-29a457cbbc90a9938f8ca3d6bf397e99b9559e58.tar.gz qemu-29a457cbbc90a9938f8ca3d6bf397e99b9559e58.tar.bz2 | |
hw/isa/lpc_ich9: Unexport PIRQ functions
No need to rely on the board to wire up the ICH9 PCI IRQs. All functions
access private state of the LPC device which suggests that it should
wire up the IRQs.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230213173033.98762-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/isa')
| -rw-r--r-- | hw/isa/lpc_ich9.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 1fba3c2..54a8839 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -259,7 +259,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) qemu_set_irq(lpc->gsi[gsi], level); } -void ich9_lpc_set_irq(void *opaque, int pirq, int level) +static void ich9_lpc_set_irq(void *opaque, int pirq, int level) { ICH9LPCState *lpc = opaque; int pic_irq, pic_dis; @@ -275,7 +275,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level) /* return the pirq number (PIRQ[A-H]:0-7) corresponding to * a given device irq pin. */ -int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) +static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) { BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); PCIBus *pci_bus = PCI_BUS(bus); @@ -286,7 +286,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; } -PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) +static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) { ICH9LPCState *lpc = opaque; PCIINTxRoute route; @@ -680,6 +680,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) { ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); DeviceState *dev = DEVICE(d); + PCIBus *pci_bus = pci_get_bus(d); ISABus *isa_bus; if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) && @@ -728,6 +729,10 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, lpc->gsi); i8257_dma_init(isa_bus, 0); + + pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS); + pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq); + pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq); } static bool ich9_rst_cnt_needed(void *opaque) |