diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-11-19 21:56:07 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-12-10 11:44:56 +0000 |
| commit | cb45adb654bb34de9de6301b6981972dd107e342 (patch) | |
| tree | 038773dc4343324f03686d818af27fb5e6b99fe9 /hw/intc | |
| parent | be9500bb17e1266ac5505a50c198397e16a56de4 (diff) | |
| download | qemu-cb45adb654bb34de9de6301b6981972dd107e342.zip qemu-cb45adb654bb34de9de6301b6981972dd107e342.tar.gz qemu-cb45adb654bb34de9de6301b6981972dd107e342.tar.bz2 | |
target/arm: Implement v8.1M REVIDR register
In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc
and is a read-only IMPDEF register providing implementation specific
minor revision information, like the v8A REVIDR_EL1. Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index be3bc1f..effc4a7 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1025,6 +1025,11 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } return val; } + case 0xcfc: + if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) { + goto bad_offset; + } + return cpu->revidr; case 0xd00: /* CPUID Base. */ return cpu->midr; case 0xd04: /* Interrupt Control State (ICSR) */ |