diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2022-05-11 20:15:21 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 10:38:50 +1000 |
| commit | c1fbcecb3a97ecce2cde5052319df34ca6bcc988 (patch) | |
| tree | 64a99ecc5aca963ee7e128c14efea08a33016ace /hw/intc | |
| parent | 075eeda93166f1914097ffb84b33df4ecc50d63c (diff) | |
| download | qemu-c1fbcecb3a97ecce2cde5052319df34ca6bcc988.zip qemu-c1fbcecb3a97ecce2cde5052319df34ca6bcc988.tar.gz qemu-c1fbcecb3a97ecce2cde5052319df34ca6bcc988.tar.bz2 | |
target/riscv: Fix csr number based privilege checking
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc')
0 files changed, 0 insertions, 0 deletions