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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-01 23:06:11 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-01 23:06:26 +0000 |
| commit | b4a8c9ae9758efb6873097f415e9972127ccf418 (patch) | |
| tree | c1d3111448f3847e7f8a5cddfa7bc3ea47d353ef /hw/intc | |
| parent | 850bbe1b94445cb84a2f648bc2e8c35ef6188eb4 (diff) | |
| parent | 5b0adce156216fb24dcc5f1683e8b686f3793fff (diff) | |
| download | qemu-b4a8c9ae9758efb6873097f415e9972127ccf418.zip qemu-b4a8c9ae9758efb6873097f415e9972127ccf418.tar.gz qemu-b4a8c9ae9758efb6873097f415e9972127ccf418.tar.bz2 | |
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into staging
target-arm queue:
* implementation of first part of the A64 Neon instruction set
* v8 AArch32 rounding and 16<->64 fp conversion instructions
* fix MIDR value on Zynq boards
* some minor bugfixes/code cleanups
# gpg: Signature made Fri 31 Jan 2014 15:06:34 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* pmaydell/tags/pull-target-arm-20140131: (34 commits)
arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
arm_gic: Introduce define for GIC_NR_SGIS
target-arm: A64: Add SIMD shift by immediate
target-arm: A64: Add simple SIMD 3-same floating point ops
target-arm: A64: Add integer ops from SIMD 3-same group
target-arm: A64: Add logic ops from SIMD 3 same group
target-arm: A64: Add top level decode for SIMD 3-same group
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
target-arm: A64: Add SIMD three-different ABDL instructions
target-arm: A64: Add SIMD three-different multiply accumulate insns
target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM
target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
target-arm: Add set_neon_rmode helper
target-arm: Add support for AArch32 SIMD VRINTX
target-arm: Add support for AArch32 FP VRINTX
target-arm: Add support for AArch32 FP VRINTZ
target-arm: Add support for AArch32 FP VRINTR
target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
target-arm: Move arm_rmode_to_sf to a shared location.
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/arm_gic.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 9409684..1c4a114 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -380,8 +380,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < 16) - value = 0xff; + if (irq < GIC_NR_SGIS) { + value = 0xff; + } + for (i = 0; i < 8; i++) { if (value & (1 << i)) { int mask = @@ -406,8 +408,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < 16) - value = 0; + if (irq < GIC_NR_SGIS) { + value = 0; + } + for (i = 0; i < 8; i++) { if (value & (1 << i)) { int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; @@ -423,8 +427,9 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < 16) - irq = 0; + if (irq < GIC_NR_SGIS) { + value = 0; + } for (i = 0; i < 8; i++) { if (value & (1 << i)) { @@ -436,6 +441,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; + if (irq < GIC_NR_SGIS) { + value = 0; + } + for (i = 0; i < 8; i++) { /* ??? This currently clears the pending bit for all CPUs, even for per-CPU interrupts. It's unclear whether this is the |