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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2022-10-31 13:25:29 +0000 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-11-08 01:04:25 +0100 |
| commit | 8063db0fc8256e3f6b9b33c246bd926f3a2dbb12 (patch) | |
| tree | f147fcacd6607a6613bc22b1b701b86ed68649c3 /hw/intc | |
| parent | cd706454c6cd239a477cb227caf3e3dfbb742d1a (diff) | |
| download | qemu-8063db0fc8256e3f6b9b33c246bd926f3a2dbb12.zip qemu-8063db0fc8256e3f6b9b33c246bd926f3a2dbb12.tar.gz qemu-8063db0fc8256e3f6b9b33c246bd926f3a2dbb12.tar.bz2 | |
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segment. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221031132531.18122-2-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/intc')
0 files changed, 0 insertions, 0 deletions