Merge tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu into staging

Third RISC-V PR for QEMU 7.2

* Update qtest comment
* Fix coverity issue with Ibex SPI
* Move load_image_to_fw_cfg() to common location
* Enable booting S-mode firmware from pflash on virt machine
* Add disas support for vector instructions
* Priority level fixes for PLIC
* Fixup TLB size calculation when using PMP

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmNJFR8ACgkQIeENKd+X
# cFTOzgf+Mg4vy3PpY/hDuYJwZyYrgcY9M/VwUFONUD5TL1ehweuEeu5NF/iJpzfP
# ywjvESxhFpGQ97zSH10IbTxQwP5fifE7JMlC4ncYTTLQYk43kiYmSM5MAbxgEC44
# PgF5/WVUWI8tDJhzfAEII17AohtTc9rzWcoXh+oLX53IB0V7qh4Eq0+Rm/i/yO5I
# oD70deU+DegHb4ka6w6k2nHEhi9IoNA0uslQrQzKVr/WQPE/1TVkmvy0u3tiFSoI
# 0MFXQjCirzdJoNU+5Wq3F0ygPMupMopOnidaMR8wH9fk3pb7hzzOve5wQRM+EtIv
# W2QGnWNaiR7n3UeGWYnh7aidcJ7Dfw==
# =O3mB
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 14 Oct 2022 03:51:59 EDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu:
  target/riscv: pmp: Fixup TLB size calculation
  hw/intc: sifive_plic: change interrupt priority register to WARL field
  hw/intc: sifive_plic: fix hard-coded max priority level
  disas/riscv.c: rvv: Add disas support for vector instructions
  hw/riscv: virt: Enable booting S-mode firmware from pflash
  hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
  hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
  hw/ssi: ibex_spi: fixup/add rw1c functionality
  hw/ssi: ibex_spi: fixup coverity issue
  hw/riscv: Update comment for qtest check in riscv_find_firmware()

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

1 files changed, 22 insertions, 3 deletions

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index af4ae36..c2dfacf 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -180,8 +180,18 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 
-        plic->source_priority[irq] = value & 7;
-        sifive_plic_update(plic);
+        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+            /*
+             * if "num_priorities + 1" is power-of-2, make each register bit of
+             * interrupt priority WARL (Write-Any-Read-Legal). Just filter
+             * out the access to unsupported priority bits.
+             */
+            plic->source_priority[irq] = value % (plic->num_priorities + 1);
+            sifive_plic_update(plic);
+        } else if (value <= plic->num_priorities) {
+            plic->source_priority[irq] = value;
+            sifive_plic_update(plic);
+        }
     } else if (addr_between(addr, plic->pending_base,
                             plic->num_sources >> 3)) {
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -205,7 +215,16 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
         uint32_t contextid = (addr & (plic->context_stride - 1));
 
         if (contextid == 0) {
-            if (value <= plic->num_priorities) {
+            if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+                /*
+                 * if "num_priorities + 1" is power-of-2, each register bit of
+                 * interrupt priority is WARL (Write-Any-Read-Legal). Just
+                 * filter out the access to unsupported priority bits.
+                 */
+                plic->target_priority[addrid] = value %
+                                                (plic->num_priorities + 1);
+                sifive_plic_update(plic);
+            } else if (value <= plic->num_priorities) {
                 plic->target_priority[addrid] = value;
                 sifive_plic_update(plic);
             }