Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging

Third RISC-V PR for 10.1

* Fix pmp range wraparound on zero
* Update FADT and MADT versions in ACPI tables
* Fix target register read when source is inactive
* Add riscv_hwprobe entry to linux-user strace list
* Do not call GETPC() in check_ret_from_m_mode()
* Revert "Generate strided vector loads/stores with tcg nodes."
* Fix exception type when VU accesses supervisor CSRs
* Restrict mideleg/medeleg/medelegh access to S-mode harts
* Restrict midelegh access to S-mode harts

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* tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu:
  target/riscv: Restrict midelegh access to S-mode harts
  target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
  target/riscv: Fix exception type when VU accesses supervisor CSRs
  riscv: Revert "Generate strided vector loads/stores with tcg nodes."
  target/riscv: do not call GETPC() in check_ret_from_m_mode()
  linux-user/strace.list: add riscv_hwprobe entry
  intc/riscv_aplic: Fix target register read when source is inactive
  tests/data/acpi/riscv64: Update expected FADT and MADT
  hw/riscv/virt-acpi-build.c: Update FADT and MADT versions
  bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes
  target/riscv: Fix pmp range wraparound on zero

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 4fa5f75..a1d9fa5 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -628,7 +628,7 @@ static void riscv_aplic_request(void *opaque, int irq, int level)
 
 static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
 {
-    uint32_t irq, word, idc;
+    uint32_t irq, word, idc, sm;
     RISCVAPLICState *aplic = opaque;
 
     /* Reads must be 4 byte words */
@@ -696,6 +696,10 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
     } else if ((APLIC_TARGET_BASE <= addr) &&
             (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
         irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+        sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
+        if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+            return 0;
+        }
         return aplic->target[irq];
     } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
             (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {